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[Embeded-SCM Develop] interleave

Description: 块交织的verilog代码--Verilog code for interleave.
Platform: | Size: 1024 | Author: | Hits:

[matlab] 信道编译码的Matlab源代码

Description: ofdm信道编码和译码的源代码，用matlab实现-OFDM channel coding and decoding of the source code, using Matlab to achieve
Platform: | Size: 75776 | Author: 张于 | Hits:

[VHDL-FPGA-Verilog] tx_inter

Description: Convolutional Interleaver Encoder-convolutional Interleaver Encoder
Platform: | Size: 1024 | Author: 孙晓伟 | Hits:

[MiddleWare] matlab_cdma

Description: 该程序仿真CDMA接收机的功能，包括解扩，解交织，信道编码(卷积码)，解码，信源编码(CRC)解码5个功能模块，生成用于数字基带传输的信号序列。 仿真CDMA发射机的功能，包括随机序列的产生，信源编码尾比特添加, 信道编码(卷积编码)，分组交织和扩频调制6个功能模块，生成用于数字基带，传输的信号序列，输出还包括用于解调所需要的信源编码尾比特值add_bits，交织器的尾比特值i_add_bits-CDMA receiver functions, including despreading, Xie intertwined, channel coding (convolutional codes), decoded, the source code (CRC) decoder five functional modules, production figures for the base band signal transmission sequence. Simulation CDMA transmitter functions, including random sequence generation, the source coding bit late add, Channel Coding (coding), a spread-spectrum modulation intertwined and six functional modules, production figures for the base-band, The transmission signal sequence, and the output is also included for the modems needed source coding bit value add_bits tail, interleaver value of the last bit i_add_bits
Platform: | Size: 3072 | Author: 刘洪 | Hits:

[assembly language] gsm_fangzheng

Description: GSM信道仿真源程序,包括各个模块(交织器,卷及码,外编码)和全信道程序-GSM channel simulation source code, including all modules (interleaver, roll and codes, encoding), and Channel procedures
Platform: | Size: 14336 | Author: fengzheng | Hits:

[Streaming Mpeg4] bit_intealeaver1

Description: verilog HDL语言实现dvb_t中的比特交织器源代码描述-verilog HDL language dvb_t the bit interleaver source code Description
Platform: | Size: 1024 | Author: wenjuner | Hits:

[Embeded-SCM Develop] turbo-interleaver

Description: 基于FPGA的Turbo码交织器的设计与实现 比较实用-FPGA-Based Turbo Code Interleaver Design and Implementation of a more practical
Platform: | Size: 371712 | Author: mediative | Hits:

[VHDL-FPGA-Verilog] veriloginterleave2

Description: 交织器的在5个源代码，:-) 对学习交织器真的很有用的啊 -Interleaver in 5 source code, :-) learning interleaver ah really useful
Platform: | Size: 11264 | Author: 吴雨彤 | Hits:

[Other] interleaver

Description: 交织代码，很好的交织验证，可以使用在很多通信场合 -Intertwined code, good interwoven authentication, you can use communication in many occasions
Platform: | Size: 1024 | Author: water206 | Hits:

[Communication] interleaver

Description: turbo码中各种交织器的设计，可以据此改编，设计出适合系统需要的交织器-a variety of turbo code interleaver design can be adapted accordingly, need to design a suitable system of interleaver
Platform: | Size: 2048 | Author: wxp | Hits:

[VC/MFC] Interleaver

Description: 用C语言编写的交织器，包括3GPP交织器，随机交织器，螺旋交织器，对角交织器，块交织，循环交织器等-Using C language interleaver, including the 3GPP interleaver, random interleaver, interleaver spiral, diagonal interleaver, block cutting, cutting cycle, etc.
Platform: | Size: 6144 | Author: 王雨 | Hits:

[Communication-Mobile] code-interleaver-decode

Description: （2，1，3）卷积码编译码程序。 每行代码有说明，方便阅读 -(2,1,3) convolutional code encoding and decoding procedures. Has made it clear that every line of code to facilitate reading
Platform: | Size: 2048 | Author: 以琳 | Hits:

[Compress-Decompress algrithms] MEET

Description: block interleaver code
Platform: | Size: 2981888 | Author: kama | Hits:

[VHDL-FPGA-Verilog] interleaver-vhdl

Description: VHDL编写的基于FPGA的4-8交织器代码，有需要的下来-4-8 prepared VHDL code interleaver
Platform: | Size: 1024 | Author: cab | Hits:

[Other] interleaver

Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Platform: | Size: 2048 | Author: tomsontiger | Hits:

[VHDL-FPGA-Verilog] interleaver

Description: 实现矩阵交织的Veriog源代码，内含有modelsim测试文件-Veriog interwoven matrix of the realization of the source code files containing the test modelsim
Platform: | Size: 27648 | Author: 尚龙 | Hits:

[3G develop] Soft_Bit_Interleaver

Description: Bit interleaver code for 3GPP LTE standard
Platform: | Size: 1024 | Author: Zol Guy | Hits:

[VHDL-FPGA-Verilog] Interleaver

Description: 自己做的交织器，里面包含了交织器的源程序，和交织器的仿真电路文件等等。。。调试后，实现结果正确-Do their own interleaver, which contains the source code interleaver and interleaver circuit simulation files and so on. . . After commissioning, to achieve the right results
Platform: | Size: 25600 | Author: luyan | Hits:

[VHDL-FPGA-Verilog] interleaver

Description: 交织编码器的verilog代码实现，此外有testbench和波形。-the verilog code for the interleave encoder, with the testbench code and waveform screen print.
Platform: | Size: 64512 | Author: Yang Jie | Hits:

[VHDL-FPGA-Verilog] interleaver

Description: vhdl code for interleaver
Platform: | Size: 1024 | Author: aruna | Hits:
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